# 电子工程代写|超大规模集成电路系统代写Introduction to VLSI Systems代考|ECE5745

## 电子工程代写|超大规模集成电路系统代写Introduction to VLSI Systems代考|Threshold-voltage of the p-type substrate

aluminum-gate MOS system, the gate-oxide thickness $t_{o x}$ is $5 \mathrm{~nm}$ and $\phi_{G S}=-0.88 \mathrm{~V}$. Assume that the acceptor concentration $N_{a}$ is $2 \times 10^{16} \mathrm{~cm}^{-3}$ and $Q_{s s}$ is $5 \times 10^{10} \mathrm{~cm}^{-2}$. Find the threshold voltage $V_{T n}$ at $T=300 \mathrm{~K}$.

Solution: At $T=300 \mathrm{~K}$, the intrinsic carrier concentration $n_{i}$ is $1.45 \times 10^{10} \mathrm{~cm}^{-3}$. From the result of the previous example and Equation (2.46), we have $Q_{d(\max )}$ as follows.
\begin{aligned} Q_{d(\max )} &=e N_{a} x_{d(\max )} \ &=1.6 \times 10^{-19} \times 2 \times 10^{16} \times 0.22 \times 10^{-4} \ &=7.04 \times 10^{-8} \mathrm{C} / \mathrm{cm}^{2} \end{aligned}
The capacitance $C_{o x}$ of the underlying MOS system is found as follows.
$$C_{o x}=\frac{\varepsilon_{o x}}{t_{o x}}=\frac{3.9 \times 8.854 \times 10^{-14}}{5 \times 10^{-7}}=6.91 \times 10^{-7} \mathrm{~F} / \mathrm{cm}^{2}$$
The threshold voltage $V_{T n}$ can be calculated from Equation (2.47) as in the following.
\begin{aligned} V_{T n} &=2\left|\phi_{f p}\right|+Q_{d(\max )} \frac{t_{o x}}{\varepsilon_{o x}}+\left(\phi_{G S}-Q_{8 s} \frac{t_{o x}}{\varepsilon_{o x}}\right) \ &=2 \times 0.37+\frac{7.04 \times 10^{-8}}{6.91 \times 10^{-7}}-0.88-\frac{5 \times 10^{10} \times\left(1.6 \times 10^{-19}\right)}{6.91 \times 10^{-7}} \ &=-0.05 \mathrm{~V} \end{aligned}
Hence, the threshold voltage is a negative value. This means that an inversion layer already exists before a positive voltage is applied to the gate.

## 电子工程代写|超大规模集成电路系统代写Introduction to VLSI Systems代考|The Operation of MOS Transistors

Now that we have understood the features of MOS systems, in this subsection we discuss the structure and operation of MOS transistors. A MOS transistor is a MOS system with the addition of two regions, referred to as the drain and source, on each side of the MOS system. The doping types of both drain and source regions are the same but opposite to the substrate. For instance, the basic structure of an nMOS transistor is shown in Figure $2.13 .$

At normal operation, the substrate is connected to a ground (i.e., $0 \mathrm{~V}$ ), a positive drain-to-source voltage is applied to the transistor, and a positive voltage is applied to the gate in order to induce an electron inversion layer at the surface of the substrate, thereby connecting both $n$-type source and drain regions. Such an inversion layer is called a channel since it provides a conductive path between source and drain regions. Because a MOS transistor has a symmetrical structure in both source and drain regions, the roles of source and drain in a circuit are determined hy the voltage applied to them. One with more positive voltage is the drain and the other is the source. It is instructive to note that the source region is the source of carriers (here are electrons; for pMOS transistors, holes), which flow through the channel to the drain region.

There are three operation modes of a typical MOS transistor. These are cut-off, linear, and saturation. In the following, we will use an nMOS transistor as an example to illustrate these three operation modes. The nMOS transistor operated in the cutoff mode is shown in Figure 2.13. As mentioned above, at the normal operation, an external positive drain-to-source voltage is applied to the transistor: At the cut-off mode, a positive voltage smaller than the threshold voltage $V_{T 0 n}$ is applied to the gate. Due to the induced electric field, a depletion layer appears at the surface of the $p$-type substrate under the silicon dioxide. Since there is no channel being induced between the source and drain regions, there is no current flowing from the drain to the source terminals.

The second operation mode of an nMOS transistor is the linear mode, as shown in Figure 2.14. In this mode, a positive voltage greater than the threshold voltage $V_{T 0 n}$ is applied to the gate of an nMOS transistor. Thereby, an electron channel is induced at the surface of the $p$-type substrate under the silicon dioxide. This channel directly connects the source to drain regions. Hence, electrons are able to flow from the source to drain regions; namely, a current flows from drain to source terminals. This current is called drain current $I_{D S}$, whose magnitude is significantly proportional to the drain-to-source voltage $V_{D S}$.

## 电子工程代写|超大规模集成电路系统代写Introduction to VLSI Systems代考|Threshold-voltage of the p-type substrate

$$Q_{d(\max )}=e N_{a} x_{d(\max )} \quad=1.6 \times 10^{-19} \times 2 \times 10^{16} \times 0.22 \times 10^{-4}=7.04 \times 10^{-8} \mathrm{C} / \mathrm{cm}^{2}$$

$$C_{o x}=\frac{\varepsilon_{o x}}{t_{o x}}=\frac{3.9 \times 8.854 \times 10^{-14}}{5 \times 10^{-7}}=6.91 \times 10^{-7} \mathrm{~F} / \mathrm{cm}^{2}$$

$$V_{T n}=2\left|\phi_{f p}\right|+Q_{d(\max )} \frac{t_{o x}}{\varepsilon_{o x}}+\left(\phi_{G S}-Q_{8 s} \frac{t_{o x}}{\varepsilon_{o x}}\right) \quad=2 \times 0.37+\frac{7.04 \times 10^{-8}}{6.91 \times 10^{-7}}-0.88-\frac{5 \times 10^{10}}{6.9}$$

## 电子工程代写|超大规模集成电路系统代写Introduction to VLSI Systems代考|The Operation of MOS Transistors

nMOS 晶体管的第二种工作模式是线性模式，如图 2.14 所示。在这种模式下，正电压大于阈值电压在吨0n应用于nMOS晶体管的栅极。从而在表面感应出电子通道p型衬底下的二氧化硅。该通道直接连接源极和漏极区域。因此，电子能够从源区流到漏区；即，电流从漏极端子流向源极端子。该电流称为漏极电流我D小号，其幅度与漏源电压显着成正比在D小号.

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