## 电子工程代写|超大规模集成电路系统代写Introduction to VLSI Systems代考|The I-V Characteristics of MOS Transistors

In the previous subsection, we have given a qualitative description of nMOS transistors. In this subsection, we explore the current versus voltage characteristics of MOS transistors.
To derive the current versus voltage characteristics of an nMOS transistor shown in Figure 2.16(a), the gradual-channel approximation (GCA) model is widely used. In this model, the following two assumptions are made.

1. The vertical electric field $E_{y}(y)$ built by $V_{G S}$ totally supports the depletion charge and the inversion layer. Here, we suppose that $V_{G S} \geq V_{T n}$ and $V_{G D}=V_{G S}-$ $V_{D S} \geq V_{T n}$.
2. The channel electric field $E_{x}(y)$ is established by the drain-to-source voltage $V_{D S}$. As a result, the channel current is only caused by the drift current due to electrons in the channel. The electron mobility $\mu_{n}$ is assumed to be constant. The boundary conditions are $V(y=0)=V_{S}=0 \mathrm{~V}$ and $V\left(y=L_{n}\right)=V_{D S}$.

Recall that an nMOS transistor is in the cut-off mode when its gate-to-source voltage $V_{G S}$ is smaller than threshold voltage $V_{T n}$. An nMOS transistor is in the linear mode when its gate-to-source voltage $V_{G S}$ is larger than threshold voltage $V_{T n}$ but the drain-to-source voltage $V_{D S}$ is a small positive voltage. In this mode, the drain current $I_{D S}$ significantly increases with the increasing drain-to-source voltage $V_{D S}$.
To quantitatively describe the drain current as a function of gate-to-source voltage and drain-to-source voltage in the linear mode, we use the $\mathrm{GCA}$ model to quantify the drain current under the strong inversion condition. According to the definition of current
$$I=\frac{d Q}{d t}$$
The drain current can be described as follows.

## 电子工程代写|超大规模集成电路系统代写Introduction to VLSI Systems代考|Channel-Length Modulation

We have supposed that the drain current $I_{D S}$ is constant when the drain-to-source voltage $V_{D S}$ reaches its saturation value $V_{D S s a t}$ and thereafter. However, the drain current $I_{D S}$ of actual devices is still slowly increased with the increasing drain-to-source voltage $V_{D S}$ after $V_{D S} \geq V_{D S s a t}$.

Referring to Figure 2.20, the depletion region at the drain end extends laterally into the channel when the MOS transistor is biased in the saturation mode, thereby reducing the effective channel length by an amount of $\Delta L$. This results in the increase of drain current $I_{D S}$ in accordance with the drain current equation. The phenomenon that the drain current is affected by the drain-to-source voltage $V_{D S}$ in the saturation region is referred to as the channel-length modulation because the effective channel length is modulated (changed) by the drain-to-source voltage.

To further quantify the amount of the increase of drain current $I_{D S}$ by the reduced channel length, we note that the reduced channel length $\Delta L$ can be related to $\Delta V_{D S}$, where $\Delta V_{D S}=V_{D S}-V_{D S s a t}$, by the following equation.
$$\Delta L=\sqrt{\frac{2 \varepsilon_{s i}}{e N_{a}}}\left(\sqrt{\left|\phi_{f p}\right|+V_{D S s a t}+\Delta V_{D S}}-\sqrt{\left|\phi_{f p}\right|+V_{D S s a t}}\right)$$
However, the above equation will make the current equation much more complicated. So in practice the following empirical relation is used instead.
$$I_{D}^{\prime}=\left(\frac{L}{I_{s}-\Delta I_{s}}\right) I_{D S}=\frac{1}{1-\lambda V_{D S}} I_{D S}$$
The resulting current equation taking into account the channel-length modulation is as follows.
$$I_{D S}=\frac{\mu_{n} C_{o x}}{2}\left(\frac{W_{n}}{L_{n}}\right)\left(V_{G S}-V_{T 0 n}\right)^{2}\left(1+\lambda V_{D S}\right)$$
where $\lambda$ is called the channel-length modulation coefficient, having a value in the range of $0.005 \mathrm{~V}^{-1}$ to $0.05 \mathrm{~V}^{-1}$

## 电子工程代写|超大规模集成电路系统代写Introduction to VLSI Systems代考|The I-V Characteristics of MOS Transistors

1. 垂直电场 $E_{y}(y)$ 由建造 $V{G S}$ 完全支持耗尽电荷和反转层。在这里，我们假设 $V_{G S} \geq V_{T n}$ 和 $V_{G D}=V_{G S}-V_{D S} \geq V_{T n}$.
2. 通道电场 $E_{x}(y)$ 由漏源电压建立 $V_{D S}$. 结果，沟道电流仅由沟道中的电子引起的漂移电流引起。电子迁 移率 $\mu_{n}$ 假定为常数。边界条件是 $V(y=0)=V_{S}=0 \mathrm{~V}$ 和 $V\left(y=L_{n}\right)=V_{D S}$.
回想一下，当 $\mathrm{nMOS}$ 晶体管的棚源电压处于截止模式时 $V_{G S}$ 小于阈值电压 $V_{T n}$. 一个 $\mathrm{nMOS}$ 晶体管在其栅 源电压时处于线性模式 $V_{G S}$ 大于阈值电压 $V_{T n}$ 但漏源电压 $V_{D S}$ 是一个小的正电压。在这种模式下，漏极电 流 $I_{D S}$ 随看漏源电压的增加显看增加 $V_{D S}$.
为了在线性模式下将漏极电流定量描述为栅源电压和漏源电压的函数，我们使用GCA模型来量化强反转条 件下的漏极电流。根据电流的定义
$$I=\frac{d Q}{d t}$$
漏极电流可以描述如下。

## 电子工程代写|超大规模集成电路系统代写Introduction to VLSI Systems代考|Channel-Length Modulation

$$\Delta L=\sqrt{\frac{2 \varepsilon_{s i}}{e N_{a}}}\left(\sqrt{\left|\phi_{f p}\right|+V_{D S s a t}+\Delta V_{D S}}-\sqrt{\left|\phi_{f p}\right|+V_{D S s a t}}\right)$$

$$I_{D}^{\prime}=\left(\frac{L}{I_{s}-\Delta I_{s}}\right) I_{D S}=\frac{1}{1-\lambda V_{D S}} I_{D S}$$

$$I_{D S}=\frac{\mu_{n} C_{o x}}{2}\left(\frac{W_{n}}{L_{n}}\right)\left(V_{G S}-V_{T 0 n}\right)^{2}\left(1+\lambda V_{D S}\right)$$

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